This invention relates to a storage device using a partial response method (or provided with a read channel) and a filter adjusting method applied to the storage device.
This application is based on Japanese Patent Application No. 9-357338, filed on Dec. 25, 1997, the contents of which are incorporated herein by reference.
Many storage devices, such as magnetic disk drives, have used a PRML (Partial Response Maximum Likelihood) method in their read channel instead of a peak detection method. In the PRML read channel, a digital equalizer (e.g., a digital filter), such as an FIR (Finite Impulse Response) filter, has been used. The FIR filter has no phase delay and plays an important role in effecting a partial response to shape the waveform digitally.
In recent years, almost all learning functions provided for LSIs including PRML read channels (PRML-LSIs) have caused FIR filters to automatically optimize a tap coefficient according to an input signal, as disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 9-21906 or U.S. Pat. No. 5,381,359.
To cause an FIR filter to perform an ideal PR (Partial Response) equalization, multiple stages of taps are needed. As the absolute value of the tap coefficient of the FIR filter becomes larger, the delay time of the digital feedback gets longer, causing a PLL (Phase Lock Loop) circuit and an AGC (automatic Gain Control) amplifier to delay stating their operations. This makes longer the time required for the PLL and AGC to settle down, which worsens the formatting efficiency of the disk considerably, because each data sector on the disk requires a preamble section corresponding to the settling time.
A method of switching between an analog loop (a loop not including an FIR filter or a digital equalizer) and a digital loop (a loop including an FIR filter or a digital equalizer) has been known as a method of preventing the formatting efficiency of a disk from deteriorating. In the method, as shown in FIG. 1, immediately after the read gate RG has turned on, the data immediately after the A/D conversion is fed back to the loop and the AGC amplifier and PLL circuit are operated; when the loop becomes stable after a certain time has elapsed, the analog loop is switched to the digital loop.
However, the method of switching between the analog loop and the digital loop has the following problem: when the analog loop is changed to the digital loop, with the absolute value of the tap coefficient of the FIR filter being large, a large error will occur in the phase.
To overcome this problem, Jpn. Pat. Appln. KOKAI Publication No. 9-21906 has disclosed the technique for estimating a phase shift resulting from the tap coefficient of an FIR filter and using a phase-shift correction FIR filter to correct a phase error occurring when the analog loop is switched to the digital loop.
The inventor of the present invention has found out the following problem: when the analog loop is switched to the digital loop, with the absolute value of the tap coefficient of the FIR filter being large, both of the PLL loop and the AGC loop become unstable, because large errors occur in not only the phase but also the amplitude (gain).
In the PRML read channel (read/write channel), since a phase error is sensed from information on the amplitude, the sensed phase error is vague, especially when a lot of amplitude errors remain (when there are many boosts at the FIR filter), aggravating the settling of the PLL and AGC.
The reason why the amplitude fluctuates at the digital equalizer will be described by reference to FIGS. 2 to 4, using a case where the digital equalizer 3 is a 3-tap FIR filter.
In the 3-tap FIR filter of FIG. 2, when a signal (input waveform) is input to the filter, the tap coefficient is set negative against to a direction for boosting, making the amplitude of the filter output (OUTPUT) smaller as shown in FIGS. 3 and 4. To compensate for the decrease in the amplitude, feedback is applied to the AGC amplifier in such a manner that the input to the FIR filter becomes larger, leading to fluctuations in the amplitude. Similarly, when the tap coefficient is set positive (when the FIR filter is forced to function as a low-pass filter), the amplitude of the filter output is larger than that of the filter input. To compensate for this, feedback is applied to the AGC amplifier in such a manner that the input to the FIR filter becomes smaller, resulting in fluctuations in the amplitude.
Almost all the present-day read channels, when the read gate RG is off, operate in a mode where the AGC amplifier is controlled at the peak value of the input waveform without operating the A/D converter or PLL circuit to save the power consumption. In such read channels, the amplitude of the output of the AGC amplifier has a larger error at the instant that the read gate RG actually turns on.
For this reason, the amplitude fluctuates at the digital equalizer when the analog loop is switched to the digital loop.
The fact that the amplitude fluctuates at the digital equalizer when the analog loop is switched to the digital loop means that the final target values of the AGC loop and PLL loop differ greatly between the digital loop and the analog loop. The difference of the final target values between the digital loop and the analog loop becomes larger in proportion to (the absolute value of) the tap coefficient of the digital equalizer. When there are variations in the characteristics of the heads (e.g. the characteristics of the heads themselves, the head's floating height), the film thickness of the recording layer of each disk (magnetic recording medium) and the magnetic characteristics of each disk, this gives rise to an extremely large or small user density (the value determined by the product of the transfer rate of the disk and the waveform width (time width) at the position of 50% of the amplitude of an isolated waveform). In this case, the absolute value of the tap coefficient of the digital equalizer becomes larger. This prevents the analog loop from switching smoothly to the digital loop, attributing to the digital equalizer's failure to learn or errors on ECC (Error Checking and Correction).